1. Field of the Invention
This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device and a method for manufacturing the same having an embedded interconnect structure in which an electrical conductor, such as copper or silver, is embedded in fine recesses formed in a surface of a semiconductor substrate, and having a protective film formed on surfaces of the interconnects to protect the interconnects.
The invention also relates to a plating solution useful for forming embedded interconnects by embedding an electrical conductor in fine recesses provided in a surface of a substrate, such as a semiconductor substrate, or for forming a protective film for protecting surfaces of embedded interconnects.
2. Description of the Related Art
As a process for forming interconnects in a semiconductor device, the so-called “damascene process”, which comprises embedding a metal (electrical conductor) into trenches and contact holes, is coming into practical use. According to this process, aluminum or, more recently a metal such as copper or silver, is embedded into trenches and contact holes previously formed in an interlayer dielectric film of a semiconductor substrate. Thereafter, extra metal is removed by chemical mechanical polishing (CMP) so as to flatten a surface of the substrate.
In recent years, instead of aluminum or aluminum alloys generally used as a material for forming interconnection circuits on a semiconductor substrate, there is an eminent movement towards using copper. This is because electric resistivity of copper, which is 1.72 μΩcm, is about 40% lower than electric resistivity of aluminum, and therefore copper interconnects suffer less from a signal delay phenomenon. Further, copper has a much higher electromigration resistance than aluminum, and is easier for use in dual-damascene processes. Thus, use of copper offers a higher possibility of providing a complicated, fine multilayer interconnection structure at a relatively low production cost.
In a case of interconnects formed by such a process, embedded interconnects have exposed surfaces after performing a flattening processing. When an additional embedded interconnect structure is formed on such an interconnects-exposed surface of a semiconductor substrate, the following problems may be encountered. For example, during formation of a new SiO2 insulating interlayer in a subsequent process for forming an interlayer dielectric film, exposed surfaces of pre-formed interconnects is likely to be oxidized. Further, upon etching of the SiO2 layer for formation of via holes, the pre-formed interconnects exposed on bottoms of the via holes can be contaminated with an etchant, a peeled resist, and the like.
In order to avoid such problems, it has been conventional to form a protective film of SiN or the like, not only on a circuit-formed region of a semiconductor substrate where surfaces of interconnects are exposed, but also on an entire surface of the substrate, thereby preventing contamination of these exposed interconnects with an etchant, and the like.
However, provision of a protective film of SiN or the like on an entire surface of a semiconductor substrate, in a semiconductor device having an embedded interconnect structure, increases a dielectric constant of an interlayer dielectric film, thus inducing delayed interconnection even when a low-resistivity material such as copper or silver is employed for interconnects, whereby performance of the semiconductor device may be impaired.
In view of this, it has been proposed to selectively cover surfaces of exposed interconnects with a protective film of Co (Cobalt), a Co alloy, Ni (Nickel) or a Ni alloy, exhibiting good adhesion to an interconnect material such as copper or silver and having a low resistivity (ρ), for example an alloy film which is obtained by electroless plating. In particular, by selectively covering surfaces of interconnects with a protective film composed of a Co—W alloy, such as a Co—W—B- or Co—W—P alloy, obtained by electroless plating, surface contamination and also thermal diffusion of the interconnects can be prevented.
However, as shown in FIG. 31, for example, when copper is embedded in trenches 4 formed in an insulating film 2 of SiO2, followed by performing a CMP processing to form copper interconnects 8, and a protective film 20 composed of a Ni—B is formed by selectively electroless plating on exposed surfaces of the copper interconnects 8 to protect the exposed surfaces of copper interconnects 8, it is difficult to equalize a film thickness of the protective film 20, and the film thickness of the protective film 20 is likely to vary widely. This wide variation of film thickness of the protective film 20 leads to a problem in that when an interlayer dielectric film is laminated onto a protective film 20 during production of multi-layer interconnects, the interlayer dielectric film cannot have a sufficiently flat surface. Further, depending upon a pattern density of interconnects, there is undesirably a case in which the protective film overhangs the insulating film 2 in a high-pattern density region.
Furthermore, depending upon pattern density and width of interconnects, there is a case in which a plating material for forming the protective film is deposited also on the insulating film, besides on the interconnects. For example, in a case of copper interconnects which have been formed by embedding copper in recesses formed in an insulating film, an elemental level of copper is generally high. Especially in a high-pattern density region, due to copper contamination of a surface of the insulating film, a plating material of electroless plating can react with copper on the insulating film, resulting in deposition thereon of the plating material.
An interconnects-protective film (cap material) is required to have a high electromigration resistance. Electromigration is considered to be caused by Joulean heat generated due to concentration of electric current, and occurs from a thin portion or a pinhole in an interconnects-protective film. In order to meet this requirement, therefore, it is desired to uniformly cover surfaces of exposed interconnects with an interconnects-protective film which is a thin, continuous film having a uniform film thickness of generally not more than 50 nm, preferably 10 to 30 nm, and which is free from a locally thin portion and a pinhole.
However, as shown in FIG. 44, when an interconnects-protective film (thin film) 20 composed of a Co—W—B alloy with a crystalline phase, having a film thickness of not more than 50 nm, is formed by electroless plating on surfaces of copper interconnects 8 which have been formed by embedding copper in insulating film 10 of SiO2, the interconnects-protective film 20 has the following problems:
The copper interconnects 8 are a poly-crystal film having a plurality of crystal orientations. Under influence of crystal orientation, a Co—W—B alloy crystal 20a with plane direction (111) grows (epitaxially) on a copper crystal 8a with plane direction (111), and a Co—W—B alloy crystal 20b with plane direction (222) grows (epitaxially) on a copper crystal 8b with plane direction (222). The Co—W—B alloy crystals 20a and 20b, with different plane directions, are different in growth rate, thereby making it difficult to obtain a continuous interconnects-protective film (thin film) having a uniform film thickness.
Thus, when an interconnects-protective film (cap material) having a crystalline phase is grown on a surface of copper, the protective film must be consistent with crystal planes of underlying copper; meaning difficulty in obtaining a uniform and continuous film, that is, difficulty in obtaining a sufficient electromigration resistance.
Further, when surfaces of interconnects are selectively covered with an interconnects-protective film composed of a Co alloy or an Ni alloy, obtained by electroless plating, to protect the interconnects, since a Co alloy or an Ni alloy is generally a magnetic material, magnetism of the interconnects-protective film can deteriorate semiconductor properties.
Moreover, when surfaces of embedded interconnects are selectively covered with a protective film (cap material) composed of a W (tungsten)-containing alloy such as a Co—W—B- or Co—W—P alloy, obtained by electroless plating, to protect the interconnects, the protective film can effectively prevent thermal diffusion of the interconnects (i.e. has an excellent thermal diffusion preventing effect). However, as shown in FIG. 55, a plating rate decreases with an increase in W concentration (W content by percentage) of the plating solution, and is thus generally lowered. In addition, a film thickness of such a plated film is sensitively influenced by a quality or state of underlying interconnects. For example, a variation in crystal orientation of the underlying interconnects can produce a remarkable variation in film thickness of the plated film and, in some cases, a uniform plated film cannot be formed on sub-micron interconnects.
On the other hand, when surfaces of embedded interconnects are selectively covered with a plated protective film (cap material) composed of a Co alloy not containing W, such as an amorphous Co—B alloy, to protect the interconnects, the plated film can be formed at a high plating rate without being influenced by a quality or state of underlying interconnects. Accordingly, a plated film having a uniform film thickness can be formed even on sub-micron interconnects. The plated film (protective film), however, cannot effectively prevent thermal diffusion of the interconnects (i.e. has a poor thermal diffusion preventing effect).
It has thus been difficult to successfully combine a requirement of using a protective film having an excellent effect of preventing thermal diffusion of interconnects, with a requirement of equalizing a film thickness of a protective film. The protective film herein refers to a film having a function of preventing thermal diffusion of underlying interconnect material, and a function of preventing oxidation of the underlying interconnect material in an oxidizing atmosphere upon formation of laminated interconnects, and also having an adequate resistance to etchants.
Copper interconnects, formed by solely using copper as an interconnect material, have enhanced electromigration resistance and stress migration resistance as compared to aluminum interconnects. With a trend toward high-speed, highly-integrated semiconductor devices, however, there is a demand for interconnects having further enhanced electromigration resistance and stress migration resistance, but not having an increased electric resistivity. With regard to a protective film of Co or a Co alloy, which is obtained by electroless plating, for selective covering and protection of interconnects, Co or a Co alloy has a higher resistivity (ρ) than copper. A demand therefore exists for decreasing a resistivity (ρ) of a protective film.